As the operating speeds of integrated circuits such as memory devices continues to increase, the timing margins for test signals applied to and received from the integrated circuits continues to decrease. For example, the period for which a digital signal is valid, known as the “eye,” decreases as the data rate increases, thereby making it more difficult for the digital signal to be acquired or captured by a receiving device during the eye. In memory systems, write data signals are normally transmitted to a memory device along with a write data strobe signal. The timing of the write data strobe signal is selected so that a transition of the write data strobe signal will occur at the center of the data eye of the write data signals. As the rate at which the write data signals are transmitted is increased, the period of the data eye is correspondingly decreased.
One factor affecting the location of the data eye is “phase jitter,” which is high frequency phase noise that causes rapid changes in the timing at which transitions of digital signals occur. Phase jitter can be caused by a number of sources, such as noise coupled to digital circuits, which causes the switching time of a digital circuit to vary in a random manner. Jitter can also be caused by variations in the propagation time of digital signals coupled through signal lines. The location of the data eye can also be affected by timing skew, duty cycle variation, and other types of unwanted signal distortion. For example, if, as is normally the case, phase jitter is present on write data signals and/or a write strobe signal coupled to a memory device, a transition of the write strobe signal may no longer occur at the center of the data eye for the write data signals. Under these circumstances, the correct write data will not be stored in the memory device. Similar problems exist in coupling other signals, such as command and address signals, to the memory device, as well as coupling read data signals and a read strobe signal from the memory device and coupling digital signals to other devices.
During the fabrication of integrated circuits such as memory devices, it is conventional to test such integrated circuits at several stages during the fabrication process. For example, the integrated circuits are normally connected to a tester with a probe card when the integrated circuits are still in wafer form. In a final test occurring after the integrated circuits have been diced from the wafer and packaged, the integrated circuits are placed into sockets on a load board. The load board is then placed on a test head, typically by a robotic handler. The test head makes electrical contact with conductors on the load board that are connected to the integrated circuits. The test head is connected through a cable to a high-speed tester so that the tester can apply signals to and receive signals from the integrated circuits.
It is important for integrated circuits to be tested under conditions that accurately simulate the conditions they will encounter in normal use. Therefore, phase jitter should be injected into signals applied to an integrated circuit in the course of testing the integrated circuit both during fabrication and after packaging. In the past, attempts have been made to inject phase jitter into test signals using various systems. A typical example of a prior art test system 10 performing this function is shown in FIG. 1. The test system 10 includes a test signal generator 14, which outputs a number of signals on a bus 16. The signals output from the test signal generator 14 may have a pattern determined by data applied to the test signal generator 14 through a JTAG interface. The number of test signals generated will determine the width of the bus 16, and both will be determined by the number of signals that a device under test (“DUT”) is adapted to receive. The test signals provided by the test signal generator 14 may be, for example, a set of memory command signals, a set of address signals, and a set of write data signals accompanied by a write data strobe signal.
The test signals coupled through the bus 16 are applied to an interface 20, which includes a register 24 for each of the test signals. Each of the registers 24 has a data input, a clock input and an output. The data input of each of the registers 24 receives a respective one of the test signals from the test signal generator 14. The output of each of the registers 24 is coupled to a respective signal line of a bus 28. The bus 28 is, in turn, connected to the DUT.
The clock inputs of all of the registers 24 in the interface 20 receive an interface clock signal ICLK from the output of a phase interpolator 30. As is well-known in the art, a phase interpolator produces a delayed signal from an input signal by shifting the phase of the input signal by a precisely controlled amount. The degree of precision of the delay of the ICLK signal depends on the precision of the input signal frequency. The phase interpolator 30 can, for example, vary the delay of the ICLK signal in 1 nanosecond increments by using an input signal having a frequency of 5 mHz and using a phase interpolator having 200 phase increments. The phase shift provided by the phase interpolator 30 is determined by a control circuit 34, which receives a phase control value at its control “C” input. The phase control value is a binary number generated by an analog-to-digital (“A/D”) converter 36. The magnitude of the phase control value corresponds to the amplitude of an analog signal applied to the input of the A/D converter 36. In the past, this analog signal has been a periodic signal, such as a sine wave.
The clock signal applied to the phase interpolator 30 is generated by a phase-lock loop (“PLL”) 38 from an input clock signal CLKIN. The PLL 38 ensures that the clock signal applied to the phase interpolator 30 has relatively little jitter and a duty cycle of substantially 50 percent.
In operation, the ICKL signal causes the test signals from the test signal generator 14 to be clocked into respective registers 20. When the test signals are clocked into the registers 24, they also become present at the outputs of the registers 24. Therefore, the transitions of the ICKL signal determines the times that the test signals are applied to the DUT through the bus 28. The sine wave applied to the input of the A/D converter 36 causes the phase interpolator 30 to increase the phase of the ICLK signal responsive to the positive portion of the sine wave and to decrease the phase of the ICLK signal responsive to the negative portion of the sine wave. As the phase of the ICKL signal increases and decreases, the timing at which the test signals are applied to the DUT also increases and decreases in a corresponding manner.
The increase and decrease in the timing at which the test signals are applied to the DUT are intended to simulate phase jitter that are expected to be present in signals received by the DUT during normal use. However, normal jitter is neither regular nor periodic. Instead, jitter is normally somewhat random, and the amplitude of the jitter varies substantially. Therefore, conventional testing systems and methods for injecting jitter in digital test signals do not accurately simulate the jitter that will be present in signals during normal operation. For this reason, a test conducted with the system 10 may indicate that the DUT will function properly under normal operation conditions, when, in fact, it may fail to function properly in normal use because of the presence of phase jitter.
There is therefore a need for a system and method that is capable of injecting phase jitter in digital test signals in a manner that causes the jitter to accurately simulate the type of jitter that is likely to be present in normal operation.